Method and Apparatus of Changing Device Identification Codes of a Memory Integrated Circuit Device

ABSTRACT

In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit.

BACKGROUND

1. Field of the Invention

This technology relates to a programmable identification code of an integrated circuit device.

2. Description of Related Art

Each memory device has an identification code to represent its memory type, density, manufacture, or even other important parameters which need to be recognized by the system. Typically the identification codes are saved by anti-fuses and unchangeable. If the memory device is replaced by another supplier or different type, the system or controller may fail, because the system or controller expects the identification code of the old replaced memory. This presents an obstacle to replacement of the memory device with another of a different type and/or a different supplier. For example, updating the hardware and or software of the system or controller with new recognition ability is time costly and time-consuming.

SUMMARY

One aspect of the technology is an integrated circuit memory device. The integrated circuit memory device includes an integrated circuit substrate, a plurality of device identification memory cells on the semiconductor substrate, a plurality of device identification selection memory cells on the semiconductor substrate, and control circuitry.

The control circuitry (i) operates a plurality of device identification codes with the plurality of device identification memory cells, the plurality of device identification codes including a plurality of bits identifying a type of the integrated circuit memory device, and (ii) operates with selection data with the plurality of device identification selection memory cells, the selection data distinguishing from among the plurality of device identification codes.

In one embodiment, the control circuitry, responsive to a device identification code read instruction, reads a device identification code from the plurality of device identification memory cells, the device identification code distinguished from other device identification codes of the plurality of device identification memory cells by the selection data of the plurality of device identification selection memory cells.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes a manufacturer identification of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes fabrication data of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes product specification data of the integrated circuit memory device.

One aspect of the technology is a method of replacing an integrated circuit memory device in an application, comprising:

-   -   providing a system configured for compatibility with a first         integrated circuit memory device type having a first device         identification code;     -   providing a second integrated circuit memory device type without         the first device identification code;     -   configuring the second integrated circuit memory device type to         have said at least part of the first device identification code;         and     -   combining the second integrated circuit memory device type with         the system.

In one embodiment said configuring includes:

-   -   programming a plurality of device identification memory cells on         the second integrated circuit memory device type with said at         least part of the first device identification code, such that         the read device identification code operation on the second         integrated circuit memory device type reads said at least part         of the first device identification code from the plurality of         device identification memory cells.

In one embodiment said configuring includes:

-   -   programming a plurality of device identification selection         memory cells on the second integrated circuit memory device type         with selection data distinguishing said at least part of the         first device identification code from among a plurality of         device identification codes on the second integrated circuit         memory device type, such that the read device identification         code operation on the second integrated circuit memory device         type reads said at least part of the first device identification         code from the plurality of device identification memory cells.

In one embodiment said configuring includes:

-   -   programming a plurality of device identification memory cells on         the second integrated circuit memory device type with said at         least part of the first device identification code, such that         the read device identification code operation on the second         integrated circuit memory device type returns to the system said         at least part of the first device identification code from the         plurality of device identification memory cells.

In one embodiment said configuring includes:

-   -   programming a plurality of device identification selection         memory cells on the second integrated circuit memory device type         with selection data distinguishing said at least part of the         first device identification code from among a plurality of         device identification codes on the second integrated circuit         memory device type, such that the read device identification         code operation on the second integrated circuit memory device         type returns to the system said at least part of the first         device identification code from the plurality of device         identification memory cells.

In one embodiment, prior to said configuring, the read device identification code operation on the second integrated circuit memory device type fails to return said at least part of the first device identification code.

In one embodiment, prior to said configuring, the second integrated circuit memory device type without the first device identification code is incompatible with the system.

In one embodiment, after said configuring, the read device identification code operation on the second integrated circuit memory device type succeeds in returning said at least part the first device identification code.

In one embodiment, after said configuring, the second integrated circuit memory device type is compatible with the system.

In one embodiment, the first device identification code includes a manufacturer identification of the integrated circuit memory device.

In one embodiment, the first device identification code includes fabrication data of the integrated circuit memory device.

In one embodiment, the first device identification code includes product specification data of the integrated circuit memory device.

One aspect of the technology is a method of manufacturing an integrated circuit memory device, comprising:

-   -   providing an integrated circuit substrate;     -   providing a plurality of application memory cells on the         semiconductor substrate;     -   providing a plurality of device identification memory cells on         the semiconductor substrate;     -   providing a plurality of device identification selection memory         cells on the semiconductor substrate; and     -   providing control circuitry that (i) programs, erases, and reads         application data with the plurality of application memory         cells, (ii) programs, erases, and reads a plurality of device         identification codes with the plurality of device identification         memory cells, the plurality of device identification codes         including a plurality of bits identifying a type of the         integrated circuit memory device, and (iii) programs, erases,         and reads selection data with the plurality of device         identification selection memory cells, the selection data         distinguishing from among the plurality of device identification         codes.

In one embodiment, the control circuitry, responsive to a device identification code read instruction, reads a device identification code from the plurality of device identification memory cells, the device identification code distinguished from other device identification codes of the plurality of device identification memory cells by the selection data of the plurality of device identification selection memory cells.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes a manufacturer identification of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes fabrication data of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes product specification data of the integrated circuit memory device.

In various embodiments, the various memory cells are nonvolatile and/or volatile.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B shows a typical memory identification code circuit implementation.

FIGS. 2A and 2B are respectively schematic and flow chart illustrations showing various embodiments of a memory identification code circuit implementation.

FIGS. 3A and 3B are schematic illustrations showing other embodiments of a memory identification code circuit implementation.

FIG. 4 shows a flow chart of how to reload and update the memory device identification code selection bit(s).

FIG. 5 shows a flow chart of how to reload and update memory device identification code bit(s).

FIG. 6 shows an example application of the changeable memory device identification selection code and the changeable memory device identification code.

FIG. 7 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

A nonvolatile memory cell (such as a flash memory device) stores data without losing data, even upon power down. Various embodiments utilize nonvolatile memory cells to store the identification codes, and can be updated by program or erase such as array data. In this way, the memory identification codes are programmable and flexible to adjust to different systems that expect different memory identification codes. Otherwise, the different systems may require disruptive and expensive changes to accommodate a new identification code of a different memory device.

FIGS. 1A and 1B shows a typical memory identification code circuit implementation. In FIG. 1A, an identification memory cell is repeated in an array structure, and output data in byte mode or word mode. A more detailed picture of the identification memory cell is shown in FIG. 1B, and includes transistors which rely on a metal layer connection to pull down the output bit line BL to ground (gnd) through the NMOS transistor, or alternatively keep the output bit line BL at supply voltage (vdd) through the PMOS transistor which weakly pulls high. Accordingly, the identification code of a memory device can be changed by modifying the metal layer of the memory device. However, this implementation is inflexible, due to the required metal layer mask change for different memory device identification codes, and the requirement of determining the memory device identification code during fabrication (and inability to change the memory device identification code after fabrication).

FIGS. 2A and 2B are respectively schematic and flow chart illustrations showing various embodiments. In FIG. 2A, each memory device identification code bit has serially connected pull down NMOS transistors, with each NMOS transistor in the series for a particular bit position being selected by the same particular bit position of the different memory device identification code selections. The upper row of NMOS transistors reads all the bit positions of the memory device identification code ID0, and the lower row of NMOS transistors reads all the bit positions of the memory device identification code ID1. For example, the leftmost serially connected pull down NMOS transistors correspond to output memory device identification code bit ID7, and within the series, the upper NMOS transistor is selected by bit position ID7 of a memory device identification code ID0, and the lower NMOS transistor is selected by bit position ID7 of another memory device identification code ID1. The dots between the upper row of NMOS transistors and the lower row of NMOS transistors indicate that, in various embodiments, the circuitry can be customized to have a particular number of memory device identification codes, i.e. a different number of rows. Also, circuitry can be customized to have a particular number of bit positions within each memory device identification code, i.e. a different number of columns.

The different memory device identification code selections are stored in nonvolatile memory and loaded into registers during power on read. If, for a particular bit position, any memory device identification code (such as the memory device ID0 code or ID1 code) is logic high, then the pull down transistor path is active for that bit position. In this way, an integrated circuit can output a selected one of multiple memory device identification codes according to one or more memory device identification code selection bits stored in one or more non-volatile memory cells. FIG. 2B shows the flowchart of the process of loading a memory device identification selection code, and then the memory device identification code selected by the memory device identification selection code, during power on read. Following power on read at 11, the memory device identification selection code is loaded from nonvolatile memory cells at 13. The memory device identification selection code is used to select one of multiple memory device identification codes at 15. Then the selected memory device identification selection code is output at 17.

FIGS. 3A and 3B are schematic illustrations showing other embodiments. FIG. 3A is memory device identification code register array structure. The registers of different memory device identification codes are enabled by the different enable signals (EN#) and output to the data bus ID0˜ID7, while the registers of other memory device identification codes that do not receive the enable signal remain inactive. FIG. 3B shows an example unit identification register which has a “Load” signal to latch the memory device identification code read from nonvolatile memory cells and the enable “EN” signal to set the latch active. Due to the memory device identification code being stored in and loaded from nonvolatile memory cells, the memory device identification code can be modified by programming or erasing the memory cell.

FIG. 4 shows a flow chart of how to reload and update the memory device identification code selection bit(s). A memory device identification selection code to be programmed is issued at 21. The program operation to program the memory device identification selection code begins at 23. Program pass or fail is determined, via a verify procedure at 25. If program fail is determined, then it is determined whether the maximum program shot number is reached at 27. If the maximum program shot number is not reached, then the program operation is repeated at 23. If the maximum program shot number is reached, then the program operation fails at 29. If program pass is determined at 25, then the algorithm proceeds with power on read at 31. The memory device identification selection code is loaded from nonvolatile memory cell(s) at 33. With the memory device identification selection code, a memory device identification code is selected at 35. The memory device identification code distinguished by the memory device identification selection code is output at 37.

FIG. 5 shows a flow chart of how to reload and update memory device identification code bit(s). A memory device identification code to be programmed is issued at 41. The program operation to program the memory device identification code begins at 43. Program pass or fail is determined, via a verify procedure at 45. If program fail is determined, then it is determined whether the maximum program shot number is reached at 47. If the maximum program shot number is not reached, then the program operation is repeated at 43. If the maximum program shot number is reached, then the program operation fails at 49. If program pass is determined at 45, then the algorithm proceeds with power on read at 51. The memory device identification selection code is loaded from nonvolatile memory cell(s) at 53. The memory device identification code is output at 55.

FIG. 6 shows an example application of the changeable memory device identification selection code and the changeable memory device identification code. A system is provided that is configured for compatibility with a 1^(st) integrated circuit memory device type having a 1^(st) device identification code at 61. Examples of compatibility are that, the system queries the 1^(st) integrated circuit memory device type, and upon receiving the 1^(st) device identification code from the 1^(st) integrated circuit memory device type, the system proceeds with regular operation. A 2^(nd) integrated circuit memory device type is provided without the 1^(st) device identification code at 63. Because, at this point, the 2^(nd) integrated circuit memory device type lacks the 1^(st) device identification code, the system is not configured for compatibility with the 2^(nd) integrated circuit memory device type. The system may even be inoperable because of this lack of compatibility. For example, the system may be configured to halt regular operation, if a query to the 2^(nd) integrated circuit type by the system fails to return the 1^(st) device identification code as expected. Without the presently described technology, such a system would have to be modified and updated to accept the different memory device identification code natively associated with the 2^(nd) integrated circuit memory device type. The 2^(nd) integrated circuit memory device type is configured to have at least part of the 1^(st) memory device identification code—minimally, at least the part of the 1^(st) memory device identification code expected by the system to continue with regular operation—at 65. Such configuration refers to updating the changeable memory device identification selection code and/or the changeable memory device identification code of the 2^(nd) integrated circuit memory device type. The 2^(nd) integrated circuit memory device type is combined with the system at 67. Such combination can occur before or after the configuration of the 2^(nd) integrated circuit memory device type.

FIG. 7 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit line 750 includes a nonvolatile memory cells with application data 700, nonvolatile memory cells with device identification codes 752, and nonvolatile memory cells with selection data 754, implemented as described herein, on one or more memory arrays. A row decoder 701 is coupled to a plurality of word lines 702, and arranged along rows in the memory array. A column decoder 703 is coupled to a plurality of bit lines 704 arranged along columns for reading and programming data from the memory cells in the array. Addresses are supplied on bus 705 to column decoder 703 and row decoder 701. Sense amplifiers and data-in structures in block 706 are coupled to the column decoder 703 in this example via data bus 707. Data is supplied via the data-in line 711 from input/output ports on the integrated circuit 750 or from other data sources internal or external to the integrated circuit 750, to the data-in structures in block 706. A controller implemented in this example using bias arrangement state machine 709 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block 708, such as read, erase, program, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.

Various embodiments use different forms of memory device parameters such as identification codes, types, densities, specifications, and so on

The programmable identification code method and apparatus according to the invention is not restricted to the application to the memory, and may also be applied to any other circuit which provides information with flexible contents.

Besides non-volatile memory cells, fuses or metal layer optional connections also can be used. The storage element can be any type of medium such as a memory cell, fuse, and metal layer connection option.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. 

1. An integrated circuit memory device, comprising: an integrated circuit substrate; a plurality of device identification memory cells on the semiconductor substrate; a plurality of device identification selection memory cells on the semiconductor substrate; and control circuitry that (i) operates a plurality of device identification codes with the plurality of device identification memory cells, the plurality of device identification codes including a plurality of bits identifying a type of the integrated circuit memory device, and (ii) operates with selection data with the plurality of device identification selection memory cells, the selection data distinguishing from among the plurality of device identification codes.
 2. The device of claim 1, wherein the control circuitry, responsive to a device identification code read instruction, reads a device identification code from the plurality of device identification memory cells, the device identification code distinguished from other device identification codes of the plurality of device identification memory cells by the selection data of the plurality of device identification selection memory cells.
 3. The device of claim 1, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes a manufacturer identification of the integrated circuit memory device.
 4. The device of claim 1, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes fabrication data of the integrated circuit memory device.
 5. The device of claim 1, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes product specification data of the integrated circuit memory device.
 6. A method of replacing an integrated circuit memory device in an application, comprising: providing a system configured for compatibility with a first integrated circuit memory device type having a first device identification code; providing a second integrated circuit memory device type without the first device identification code; configuring the second integrated circuit memory device type to have said at least part of the first device identification code; and combining the second integrated circuit memory device type with the system.
 7. The method of claim 6, wherein said configuring includes: programming a plurality of device identification memory cells on the second integrated circuit memory device type with said at least part of the first device identification code, such that a read device identification code operation on the second integrated circuit memory device type reads said at least part of the first device identification code from the plurality of device identification memory cells.
 8. The method of claim 6, wherein said configuring includes: programming a plurality of device identification selection memory cells on the second integrated circuit memory device type with selection data distinguishing said at least part of the first device identification code from among a plurality of device identification codes on the second integrated circuit memory device type, such that a read device identification code operation on the second integrated circuit memory device type reads said at least part of the first device identification code from the plurality of device identification memory cells.
 9. The method of claim 6, wherein said configuring includes: programming a plurality of device identification memory cells on the second integrated circuit memory device type with said at least part of the first device identification code, such that a read device identification code operation on the second integrated circuit memory device type returns to the system said at least part of the first device identification code from the plurality of device identification memory cells.
 10. The method of claim 6, wherein said configuring includes: programming a plurality of device identification selection memory cells on the second integrated circuit memory device type with selection data distinguishing said at least part of the first device identification code from among a plurality of device identification codes on the second integrated circuit memory device type, such that a read device identification code operation on the second integrated circuit memory device type returns to the system said at least part of the first device identification code from the plurality of device identification memory cells.
 11. The method of claim 6, wherein prior to said configuring, a read device identification code operation on the second integrated circuit memory device type fails to return said at least part of the first device identification code.
 12. The method of claim 6, wherein prior to said configuring, the second integrated circuit memory device type without the first device identification code is incompatible with the system.
 13. The method of claim 6, wherein after said configuring, a read device identification code operation on the second integrated circuit memory device type succeeds in returning said at least part the first device identification code.
 14. The method of claim 6, wherein after said configuring, the second integrated circuit memory device type is compatible with the system.
 15. The method of claim 6, wherein the first device identification code includes a manufacturer identification of the integrated circuit memory device.
 16. The method of claim 6, wherein the first device identification code includes fabrication data of the integrated circuit memory device.
 17. The method of claim 6, wherein the first device identification code includes product specification data of the integrated circuit memory device.
 18. A method of manufacturing an integrated circuit memory device, comprising: providing an integrated circuit substrate; providing a plurality of device identification memory cells on the semiconductor substrate; providing a plurality of device identification selection memory cells on the semiconductor substrate; and providing control circuitry that (i) operates a plurality of device identification codes with the plurality of device identification memory cells, the plurality of device identification codes including a plurality of bits identifying a type of the integrated circuit memory device, and (ii) operates with selection data with the plurality of device identification selection memory cells, the selection data distinguishing from among the plurality of device identification codes.
 19. The method of claim 18, wherein the control circuitry, responsive to a device identification code read instruction, reads a device identification code from the plurality of device identification memory cells, the device identification code distinguished from other device identification codes of the plurality of device identification memory cells by the selection data of the plurality of device identification selection memory cells.
 20. The device of claim 18, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes a manufacturer identification of the integrated circuit memory device.
 21. The device of claim 18, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes fabrication data of the integrated circuit memory device.
 22. The device of claim 18, wherein the type of the integrated circuit memory device identified by a device identification code of the plurality of device identification codes, includes product specification data of the integrated circuit memory device. 